In a current LSI, a multilayer wiring structure is generally applied. The wiring structure is made up by including a wiring part extending in a lateral direction on an interlayer insulating film and a via part in a vertical direction which fills a via hole of the interlayer insulating film with a conductive material, and electrically connects the wiring parts (between wirings at up and down). Copper (Cu) is mainly used as a wiring material of a leading-edge semiconductor device, and it is general to form the via part by filling and so on a metal material such as Cu in the via hole formed at a predetermined position so as to conduct with Cu wirings.
In recent years, it has been studied to use a carbon material including a cylindrical structure of carbon represented by so-called a carbon nanotube (CNT), a cylindrical carbon fiber, and so on in addition to the metal material such as Cu at the via part. In particular, the CNT has various properties such as excellent in chemical stability, and having peculiar physical and electrical characteristics, and so on, and therefore, it is watched as a forming material of a semiconductor device. As for the CNT, various studies have been continued up to now, for example, a forming position control, a chirality control, and so on in addition to controls of a size and a length thereof.
There is a configuration in which the wiring part of Cu is formed via a barrier film of Ta and so on which prevents Cu diffusion so as to cover the CNTs protruding from the via hole in the wiring structure using the CNTs at the via part (refer to Patent Literature 1, Non-Patent Literature 1). Besides, a configuration in which the wiring part is formed by using the CNTs is also proposed (Patent Literature 2). Further, a configuration in which a wiring is formed by using graphene, in particular a multilayer graphene is also proposed (Non-Patent Literature 2).
Patent Literature 1: Japanese Patent No. 4212258
Patent Literature 2: Japanese Laid-open Patent Publication No. 2008-251701
Non-Patent Literature 1: Nihei et al., Japan Journal of Applied Physics, Vol. 43 (2004) p. 1856
Non-Patent Literature 2: A. Naeemi and J. D. Meindl: Proc. of the 11th IEEE IITC (2008) p. 183
Non-Patent Literature 3: D. Kondo et al., Appl. Phys. Express, Vol. 3 (2010) p. 025102.
Non-Patent Literature 4: A. Reina et al., Nano Lett. Vol. 9 (2009) p. 30.
As stated above, the wiring structure in which the CNTs are used at the via part and the graphene is used at the wiring part is extremely effective for the LSI. However, there is a problem to be solved to enable the above. Actually, it is impossible to secure an enough electrical contact between the CNTs and the graphene only by overlapping the graphene on the CNTs. It is because a good connection is difficult to obtain only by pressing the CNTs and the graphene.